As a circuit designer, it’s good to read, to know, or to think about the trends in his/her domain. It was sooo late that I came to realize it ):. However, I, fortunately, anyway, realized its importance and made up my mind to be a doer.
Let me start from the paper written by B. Nauta, titled ‘Analog/RF circuit design techniques for nanometerscale IC technologies.’ (published in ESSCIRC, 2005)[pdf]
Based on my preference, I extract some interesting points from his paper, most of which keep a form as Q&A.
1) What is the motivation of the evolution in CMOS technology?
Decreasing price-per-performance for digital circuitry. It’s pace is determined by Moore’s Law.
2) Why is the dimension-shrink accompanied by lowering the nominal supply voltages?
To ensure sufficient lifetime for digital circuitry and to keep power consumption at an acceptable level.
As we might know, the scaling brings benefits to the digital part, but it also introduces problems to the analog part, such as degraded signal-to-noise ratio. In this paper, the author intensively discusses the design issues related with gate leakage effects, which is one of the relatively new effects in ultra-deep submicron CMOS.
3) What are the major influences to analog design brought by gate-leakage?
a. It poses a lower limits to the usable frequency range for integrator circuits.
b. It introduces a strong relation between DC-current gain and transistor length.
c. Its mismatch introduces a new limit to achievable accuracy.
d. It introduces shot-noise.
Contemporary ICs are mixed-signal systems consisting of a large digital core and analog interface blocks such as I/O, data converters, and RF front ends. It’s cost-saving if all these functions can be integrated on a single die. So we inevitably will meet with the following questions:
4) What’s the analog challenge from a system point of view?
The challenge can be split into two directions: 1) move to higher frequencies to use the advanced technology, such as 60GHz communications and radar; 2) to achieve both higher programmability and flexibility for multiple standards RF by digitizing RF sections, e.g. software radio.
5) How to understand ‘analog circuits for digital’?
First, pure digital ICs contain a few basic analog functions such as power-on-reset and a PLL for internal high speed low jitter clock generation.
Second, pure digital circuits face the problem of signal integrity, where proper on-chip decoupling is needed to solve the problem at the cost of area.
Third, to minimize the power consumption, adaptive supply voltages and clocks can be used to the digital blocks.
Fourth, to overcome the process and temperature variations, analog control for digital circuits is emerging like sensory electronics in large digital ICs.
Fifth, sixth, seventh, …
6) How to understand ‘digital circuits for analog’?
Non-ideal effects of analog circuits can be calibrated in the digital domain. This trend of calibrating is clearly observable in AD converters (which is one of my research interests, and it might worth more deep and thorough discussions in later posts).
7) Will purely digital and analog blocks disappear?
This is a very interesting question. Since the strive towards higher circuit performance out of less perfect transistors yields a trend towards analog control for digital and towards digital control for analog, it seems both purely digital and analog blocks will disappear.
Anyway, as a fan of analog design, I believe that the knowledge related with analog circuits will be always useful, even if we are surrounded by purely digital gates. However, please also keep a keen eye on the other side of your design world simultaneously, for you can’t live without them either (: .