Pacemaker C: ADC Related

My design of an ultra-low power ultra-low speed ADC is for pacemakers. However, since I’m focusing on the design of stand-alone ADC, I somewhat neglect the exact requirement from the perspective of pacemaker system (I know it’s not good, but research could have such excuse (:).

In this post, I try to ask myself several questions related with ADC design from the view of pacemaker system. Just for a moment, forget about research, about beating the performance numbers without thinking the real world (:

1. How many number of bits are required?

This is related to the minimum and maximum signal the ADC is going to digitize. Since the pacemaker deals with the heart, an example of the well-known surface electrocardiogram (ECG) is shown in Fig.1. The ECG signal can be as small as several tenths of mV for smaller components like the P-wave to tens of mV in amplitude for the largest features in a QRS complex [1]. So the resolution required is usually no less than 8 bits.

Fig.1 Surface ECG showing the various components of the cardiac cycle (Curtsey:Wiki))

2. What’s the sampling frequency?

The frequency range of ECG is from several tenths of 1Hz to tens of 100Hz. The sampling rate of ADC is around 1kS/s [2].

3. Any system clock provided in the pacemaker?

There is a clock generation subsystem provides different frequencies of clocks for the pacemaker, which is typically based on a 32kHz crystal.

4. Can multiple supplies be used in ADC?

There is a power management subsystem, which includes regulators to provide different levels of voltages for other subsystems, and detectors to measure the battery voltage when it has reached the elective replacement interval (ERI) or end of service (EOS) points.

Multiple voltage scheme can be used inside the pacemaker to achieve high power efficiency. For example, higher supplies are used by pace drivers to provide a larger signal swing and high gate drive to analog swiches. Digital functions, on the other hand, benefit from lower supplies to reduce both dynamic and leakage power consumption. Moreover, the regulators may also have standby mode to allow a function to retain its state with a lower voltage.

5. What’s the power consumption of ADC?

To answer this question, let us first look at the capacites of pacemaker batteries. Usually it’s on the order of 900 mA-hrs, which translates into approximately 100 uA-years [1]. This means if the life span of pacemaker is 10 years, the average current drawn by a pacemaker should be no less than 10 uA. This simplified example highlights that if we save a block for 100 nA current consumption, we increase the longevity of the device by over one month!


[1] H.-J. Yoo and C. van Hoof, Bio-Medical CMOS ICs, Springer, 2011

[2] L S. Y. Wong, et al., A very low-power CMOS mixed-signal IC for implantable pacemaker applications, JSSC, 2004.

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