I watched 3D Kung Fu Panda 2 last Sunday. Yeah, 3D! I still remember the state of great excitement the first time when I sat in a cinema for a 3D movie 18 years ago, watching a huge stone running towards me.
Back from panda, to the world of KungFu Electronics, recently I saw many articles talking about Intel’s 3D transistors. Though not an enthusiast of process, I ‘m still likely to know what the story is all about. My ‘inner peace’ encourages me to read some articles related to it.
As usual, I use some Q&As to help myself digest some basic contents.
1. Visualize the tri-gate transistor?
2. Which technology node it is for (according to Intel)?
Though 3D looks really cool, we might still ask why it has to be bothered to go for 3D. Does nothing can be done for direct scaling anymore? OK, to answer this question, let’s first go for a basic question to scaling:
3. What’s the important performance metric of transistor together with scaling?
Active transistor saturation drive current (Idsat).
(For a better explanation, refer to [IEDM 2005: Selected Coverage].)
4. What are other kinds of KungFu with scaling before entering the 3D regime?
As I indicated with ‘Red’ in the above figure, there are: feature size scaling (Lgate & tox), stressed silicon, and metal gate electrodes along with high-K gate oxides.
Two related terms (courtsey: Intel):
Strained silicon – A technique for speeding up transistors. As described above, the silicon atoms in the channel are packed neatly in a grid-like (lattice) structure. It has been known for decades that stretching the grid so the silicon atoms are slightly farther apart than in their natural state makes NMOS transistors switch faster (similarly, compressing the lattice slightly speeds up PMOS transistors). This stretching/compressing is known as straining. Intel uses special techniques to strain its 90nm process NMOS and PMOS transistors to improve their performance.
High-k material – A material that can replace silicon dioxide as a gate dielectric. It has good insulating properties and creates high-field effect (hence the term “high-k”) between the gate and channel. Both are desirable properties for high-performance transistors. “k” (actually the Greek letter kappa) is an engineering term for the ability of a material to hold electric charge. Think of a sponge: it can hold a lot of water. Wood can hold some, but not as much. Glass can’t hold any at all. Similarly, some materials can store charge better than others, and hence have a higher “k” value. Also, because high-k materials can be thicker than silicon dioxide – while retaining the same desirable properties – they greatly reduce leakage.
5. Any critical issue I still miss till now?
Yes, Leakage! Since the tri-gate has a better control of the channel (3!), the leakage is not as severe as traditional scaling. For more details, please have a look at the comparison between tri-gate and planar 65nm transistors from Intel [Integrated CMOS Tri-Gate Transistors (Figure 2)].
Hence, for scaling, two factors are critical: low Ioff + high Idsat. Low Ioff leads to good power efficiency and high Idsat speeds up the circuit.
6. At these smallest process nodes, is it totally impossible if we keep scaling the planar transistor?
Of course not, but there are just too many compromises, such as large leakage current and threshold variation. Since geometries get small, the number of dopant atoms per transistor is also small and even one dopant atom more or less creates parametric variations.The only way to overcome this variation is overdesign.
EveryAtom Counts (;
Are FinFETs inevitable at 20nm? This article is worth reading if you want to know more about the story.
7. Additional cost for manufacturing?
It only takes one extra mask to create the silicon fin, which shows its high compatibility with contemporary advanced CMOS manufacturing techniques.
Since I’m really not good at (or interested in) physics, I will stop the topic here. Much information from www can be searched if you are a fan of it. However, there is still a question left, a final, an ultimate question:
8. As a circuit designer, what kind of KungFu I need to practice at smaller geometries?
a. You have to understand the underlying physics (sad answer to myself).
b. You need to think probabilistically, rather than deterministically, since variability is one of the biggest challenges to high yield.
c. …maybe inner peace! (;