## The EKV MOS Model

Recently I’m referring some papers about low-voltage amplifiers. I came to know the EKV MOS model, which is mainly dedicated to low-voltage and low-current analog design. Then I read a short history of the EKV model written by one of the model developers, C. C. Enz. In order to know a little bit more about the model details, I read the authors’ 1995 paper[1], a seminal paper which fully talked about the model and also  gave its name to the model.

Reading that kind of paper, mainly dealing with physics and sometimes mathematics, yes, is a little bit painful.

The beauty of the EKV model to me is symmetry, continuity, and simplicity.

• Symmetry

Fig. 1 NMOS transistor with all voltages referred to the local substrate (bulk).

Different from BSIM model, where all the voltages are referred to the source terminal, in the EKV model, the source, the drain, and the gate voltages are all referred to the local substrate. Bulk reference allows the model to be handled symmetrically with respect to source and drain (a symmetry that is also inherent in CMOS technologies).

• Continuity

The EKV model describes the behavior of the transistor in a continuous manner from low currents (weak inversion, moderate inversion) to large currents (strong inversion).

The drain current is derived and expressed as the difference between a forward component and a reverse component. It is exponential in weak inversion and quadratic in strong inversion. The current in moderate inversion is modeled using an appropriate interpolation function resulting in a continuous expression valid from weak to strong inversion [1].

The inversion coefficient (IC):

$IC = \frac{I_D}{I_0(\frac{W}{L})}$,

where the technology current $I_0$ is given by $IC = 2 \cdot n_0 \cdot \mu \cdot C_{OX} \cdot U ^2_T$. The inversion coefficient results in linear relationships between the drain current and transistor sizing based on the normalization to a fixed technology current. Weak inversion corresponds to IC < 0.1, moderate inversion corresponds to 0.1 < IC < 10, and strong inversion corresponds to IC > 10.

Using the inversion coefficient enables analog design and design optimization freely in all regions of inversion. Fig. 2 illustrates estimated values of VDSAT and (VGS-VT) for its respective IC, in order to provide comparison between different operation modes (weak/moderate/strong). Fig. 3 also shows the estimated gm/ID as a function of IC using.

Fig. 2 VDSAT and (VGS-VT) as a function of IC [2]

Fig.3 gm/ID as a function of IC [3]

The general methodology based on inversion coefficient:

Fig.4 General procedure of inversion coefficient based design methodology

To get a more detailed feeling about design analog circuits using inversion coefficient based on the EKV model, [2] could be a good reference. In addition, [3] is also a nice paper, which talks about tradeoffs and optimization in analog CMOS design using the EKV model.

• Simplicity

Simplicity here mainly means fewest parameters. “This model has only 9 physical parameters, 3 fine tuning fitting coefficients, and 2 additional temperature parameters [1].” 9+3+2 = 14, yes! Moreover, it makes analog design possible to be optimized by a spreadsheet or a Matlab script.

Last but not least, one model may not be the answer for everything.

Reference

[1] Enz, C. C., Krummenacher, F., Vittoz, E.A., “An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications”, Analog Integrated Circuits and Signal Processing Journal on Low-Voltage and Low-Power Design, July 1995.

[2] D. M. Colombo, G. I. Wirth, and C. Fayomi, “Design methodology using inversion coefficient for low-voltage low-power CMOS voltage reference”, Proc. 23rd Symp. on Integrated Circuits and System Design, pp. 43-48, 2010.

[3] Binkley, D.M. , “Tradeoffs and Optimization in Analog CMOS Design,” Mixed Design of Integrated Circuits and Systems, June 2007.

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### 3 Responses to The EKV MOS Model

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