Brief Study of Dither C: Dithered DNL

In ‘Dither’ series B, I have shown dither reduces the harmonic distortion by decolalizing the code mapping of the analog signal from the transfer curve. So if we take a step further, we might say the main purpose of dither is to randomize the DNL errors of the converter.

Then, it seems that DNL is kind of related to harmonic distortion. In ‘ADC performance’ series A, I discussed the relationship between DNL and SNR. In that post, I have taken the DNL error as uniformly distributed noise. However, the story told by the DNL plot could not be that simple. In this post, I will try to explain more about DNL, of course, together with a further discussion of the dither.

1. Dynamic effects of DNL from distortion point-of-view

The location of DNL error is important. For example, shown in Figure 1, a converter may have a DNL error of +2 LSB at code(–FS), which is a quite large error. However, its effect will be minimal for a converter which rarely uses codes near full scale. Conversely, a converter may have a DNL error of +0.25 LSB for 4 codes near midscale, which indicates +1 LSB of transfer function error around that location. If a converter repetitively works in the middle range, the four errors will cause potential dynamic distortions.

Figure 1. The location of the DNL error is important [1].

Figure 1. The location of the DNL error is important [1].

Thus a blanket statement about the INL or DNL of a converter without additional information (location, frequency, etc.) is almost useless [1].

2. Dithered DNL – An example of a subranging pipelined ADC from ADI [2]

The 14-bit 105-MSPS AD6645 block diagram:

Figure 2. The block diagram of AD6645 from ADI.

Figure 2. The block diagram of AD6645 from ADI.

The problem – the significant DNL error occur at the ADC1 transition points:

Figure 3. AD6645 subranging point DNL errors (exaggerated).

Figure 3. AD6645 subranging point DNL errors (exaggerated).

The solution – a peak-to-peak dither noise cover about two ADC1 transitions is added to the input. The DNL is not significantly improved with higher levels of noise.

The result – undithered DNL versus dithered DNL:

Figure 4. AD6645 undithered and dithered DNL.

Figure 4. AD6645 undithered and dithered DNL.

I will end the discussion of dither till this point. I wish I could have some chance to try the dither method in the future and have a better understanding of it. Though 3 posts written, I’m still a little bit puzzled with dither…It’s really not that easy to deal with noise!

Reference

[1] Brad Brannon, Overcoming converter nonlinearities with dither, Analog Devices, AN-410.
[2] Walt Kester, The good, the bad, and the ugly aspects of ADC input noise – is no noise good noise?  Analog Devices,  MT-004.

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4 Responses to Brief Study of Dither C: Dithered DNL

  1. Domenico says:

    Good article 😉

    (There is a typo in the first line “decolalizing” instead of “delocalizing”).

  2. Anonymous says:

    mei zhi, you are very niu.

  3. 3Sigma says:

    Hi
    You’ve a nice blog here.
    I’ve also started blogging about analog design with emphasis on ADC design.
    Please check out my blog http://analogquantized.wordpress.com/

    Thanks
    3Sigma

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