The 1st post in 2013. Happy middle new year! 😉

Nowadays most of us in academy are designing analog circuits in deep-submicron nodes using short-channel transistors. Putting them together with the digital, building up a system, and selling it with extraordinary performance in top conferences or journals—that’s a dream (sometimes triggers a real nightmare) of a PhD student…

Then do you miss the old time when you are designing circuits using long-channel transistors?

I miss! The square-law equation is so neat that the relation among the drain current, the effective voltage, and the transconductance can simply be expressed by

With certain effective gate-source voltage, the transconductance linearly follows the biasing current. It is quite straightforward to tell how much power you will pay for your target gain.

Soon, the short-channel transistors together with low voltage come ;-). Life becomes not that straightforward. In [1] and [2], the authors introduce a parameter *Veff*, defined by

They also compare their parameter with the square-law equation using the following figure.

Fig. 1 Veff versus VGS-VT [1][2].

Yes! For modern short-channel transistors, they are often biased in the transition region between sub-threshold and saturation regions. They are making classical equations useless! The proposing of

*Veff* is so decent that it provides a simple way for us to analyze the power bounds of analog circuits in modern CMOS [1][2].

If you ponder on the above simulated curves, do you remember something which also has the beauty of simplicity and continuity?

Yes. The EKV model! In this model, the *Veff*, using inversion coefficient, can be derived by [3]

And the effective gate-source voltage is expressed as [3]

Out of curiosity, I plotted Veff versus VGS-VT based on the EKV model, together with the simulated curves, which I obtained using a similar method as used in [1][2] but for different processes. The figure is shown as bellow.

Fig. 2 Veff versus VGS-VT with EKV model included (Different inversion regions are also indicated).

Though the analog world can’t be as simple as **0** or** 1**, still the simpler the better!

**Reference**

[1] T. Sundström, B. Murmann, and C. Svensson, “Power dissipation bounds for high-speed Nyquist analog-to-digital converters”, *TCASI*, 2008.

[2] C. Svensson and J. J. Wikner, “Power consumption of analog circuits: a tutorial”, *Analog Springer*, 2010.

[3] D. M. Binkley, B. J. Blalock, and J. M. Rochelle, “Optimizing drain current, inversion level, and channel length in analog CMOS design”, *Analog Springer*, 2006.

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