Brief Study of Noise-Shaping SAR ADC – Part B

In the previous post, I’ve shared some basics of sigma-delta ADC. In this post, before we look at the noise-shaping SAR ADC, let’s again do a warm-up.

The z-domain linear model for a 1st-order sigma-delta modulator:

Fig.1 Linear model of a 1st-order sigma-delta modulator

The linear model has the same transfer functions as the one in Fig.6 of the previous post, where a delaying integrator is used as the loop filter.

Before the quantizer, the modulator is doing two tasks:

1. Δ: generate the conversion residue R (=U-V)

2. ∑: add all the previous residues

Keep this in mind. Now let’s try to make the SAR do the noise shaping.

A conventional charge-redistribution SAR ADC:

Fig. 2 Charge-redistribution SAR ADC

When the conversion is complete for an N-bit SAR, the magnitude of the voltage generated at the top plate of the DAC represents the difference between the sampled input and a representation constructed from decisions of the high-weighted N-1 bits:

$V_{DAC} = \frac{V_{REF}}{2}D_{N-1}+\frac{V_{REF}}{2^2}D_{N-2}+\cdots+\frac{V_{REF}}{2^{N-1}}D_1-V_{IN}$

If we do one extra switching of the DAC array based on the final decision of LSB, we recalculate the voltage generated at the DAC top plate:

$V_{DAC}^{+1} = \frac{V_{REF}}{2}D_{N-1}+\cdots+\frac{V_{REF}}{2^{N-1}}D_1+\frac{V_{REF}}{2^N}D_0-V_{IN}$

Yes! We catch the conversion residue! It is further simplified as follows:

$V_{RES} = D_{OUT}-V_{IN}$

According to Fig.1, the simplified equation can be rewritten as $-V_{RES} = V_{IN}-D_{OUT}$ .

Then we need to sample this residue and store it somewhere else. How about this method?

Step 1: sample the residue on the extra capacitor

Fig.3 Sample the residue on the extra capacitor (discrete-time domain is used to indicate the current sample and the previous one)

Step2: apply the sampled residue to the opposite input of the comparator during the next conversion

Fig.4 Apply the residue to the opposite input of the comparator when the next sample is converted

Now it comes to the discussion about choosing the value of C_R.

Assume $C_R = k C_{DAC}$

Then $V_R(n) = k_1 V_{RES}(n) + k_2 V_R(n-1)$ ,

$k_1=\frac{1}{1+k}$ and $k_2=\frac{k}{1+k}$

What will the linear model look like?

Fig. 5 Linear model and transfer functions

If $C_R << C_{DAC}$ ( $k \approx 0$ ), $k_1 \approx 1$ and $k_2 \approx 0$ . The memory of the previous residues is ignored and only the current residue is recorded. The linear model can be simplified to:

Fig. 6 Linear model and transfer functions when k1=1 and k2=0

Take a look at the magnitude responses of the NTFs under different k:

Fig. 5 Magnitude response of NTFs under different k and 1st-order noise shaping

Fig. 5 Magnitude response of NTFs under different k and compared to 1st-order noise shaping

Noise does be shaped! In addition, it seems using a small residue sampling capacitor is fairly good compared to larger ones (Note that the kT/C noise during residue sampling presents itself to the comparator input and can also be shaped together with the quantization noise and the input-referred comparator noise [1]).

However, compared to the 1st-order modulator, this way of noise shaping is much less efficient. We could do better! How? The next post ;-).

References:

[1] J. A. Fredenburg and M. P. Flynn, “A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-shaping SAR ADC”, JSSC, vol.47, 2012.

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