Either Prof. Sansen’s inversion coefficient (IC) approach or Prof. Murmann’s Gm/Id design methodology is telling the same story of power-aware analog design.
With the help of Gm/Id design kit, I can easily visualize the transistor performance as a function of its gate-source voltage (see Fig.1). As VGS increases, the transistor undergoes the weak, the moderate, and the strong inversion. For high gain, we go left; for high speed, we go right. Being far-left, the gain is not increasing but the speed drops extremely low; being far-right, the speed is not increasing but the drain current is still climbing! For a decent figure-0f-merit (speed*gain), go to the middle, go moderate!
As CMOSers, we love the square-law equation, we sometimes hate and sometimes embrace the exponential subthreshold current equation. But with regard to the current flowing between the strong and the weak, do we have one equation for it? No, but yes…by doing some math, the EKV model combines all the three. Referring to , the IC-V related equations are copied as follows:
where n is subthreshold slope factor and UT is thermal voltage. At room temperature, 2nUT is about 70mV . As Fig.2 shows, the IC-V curve matches well with the weak for IC < 0.1 or the strong for IC > 10; the moderate locates where IC is between 0.1 and 10.
 W. Sansen, “Minimum power in analog amplifying blocks – presenting a design procedure ”, IEEE Solid-State Circuits Magazine, fall 2015.
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