A Brief Review On the Orders of PLL

The simplest PLL, as is shown in Fig.1, consists of a phase detector (PD) and a voltage controlled oscillator (VCO). Via a negative feedback loop, the PD compares the phases of OUT and IN, generating an error voltage that varies the VCO frequency until the phases are aligned.

simplestPLL
Fig.1 A 1st-order PLL

This topology, however, must be modified because the output of PD consists of a dc component (desirable) and high-frequency components (undesirable). The control voltage of VCO must remain quiet in the steady state, which means the PD output should be filtered. Therefore, a 1st-order low-pass RC filter is interposed between the PD and the VCO, as is shown in Fig.2.

2ndLPF
Fig.2 A 2nd-order PLL with a low-pass RC filter

PLLs are best analyzed in the phase domain (Fig.3). It is instructive to calculate the phase transfer function from the input to the output. The ideal PD can be modeled as the cascade of a summing node and a gain stage, because the dc value of the PD output is proportional to the phase difference of the input and output. The VCO output frequency is proportional to the control voltage. Since phase is the integral of the frequency, the VCO acts as an ideal integrator which receives a voltage and outputs a phase signal.

phasemodel
Fig.3 The phase domain model of PLL

The overall loop transfer function of the 2nd-order PLL shown in Fig.2 can be written as

\frac{\phi_{out}(s)}{\phi_{in}(s)}=\frac{K_P K_V \omega_{RC}}{s^2+\omega_{RC}s+K_P K_V \omega_{RC}}

where \omega_{RC}=1/RC. The phase error has the following transfer function

\frac{\phi_{e}(s)}{\phi_{in}(s)}=\frac{s^2+\omega_{RC}s}{s^2+\omega_{RC}s+K_P K_V \omega_{RC}}

If the input is a sinusoidal of constant angular frequency ωi, the phase ramps linearly with time at a rate of ωi. Thus, the Laplace-domain representation of the input signal is \phi_{in}(s) = \omega_i / s^2. From the final value theorem, the steady-state phase error is

\Phi_e(t=\infty) = \lim_{s \to 0} s \Phi_e(s) = \frac{\omega_i(s+\omega_{RC})}{s^2+\omega_{RC}s+K_P K_V \omega_{RC}} = \frac{\omega_i}{K_P K_V}

As can be seen, to lower the phase error, KpKv must be increased. Moreover, as the input frequency of the PLL varies, so does the phase error. Subsequently, in order to eliminate the phase error, a pole at the origin can be introduced. The RC loop filter can then be replaced by an integrator. Hence, it comes the popular architecture – charge-pump PLL (Fig.4), which comprises a phase/frequency detector, a charge pump, and a VCO.

2ndCP
Fig.4 A 2nd-order CPPLL

As long as the loop dynamics are much slower than the signal, the charge pump can be treated as a continuous time integrator. The phase model of CPPLL is now shown in Fig.5. Writing the transfer function and doing some calculation, the phase error is finally confirmed to be eliminated. However, one must remember that two integrators are now sitting in the forward path, each contributing a constant phase shift of 90°. It will be frightening to see the phase curve is a straight line at -180° for a negative feedback system.

phasemodel_cppll

Fig.5 Phase model of simple CPPLL

In order to stabilize the system, a zero is introduced by adding a resistor in series with the charge pump capacitor (Fig.6). Placing the zero before the gain crossover frequency helps to lift the phase curve up.

2ndCPwithzero
Fig.6 A 2nd-order CPPLL with a zero

The compensated PLL suffers from a critical drawback. Each time a current is injected into the RC branch, the control voltage to the VCO will experience a large jump. Even in the locked conditions, the mismatches between charge and discharge current introduce voltage jumps in the control voltage. The resulting ripple disturbs the VCO. To relax this issue, a second capacitor is commonly tied between the control line and ground (Fig.7).

3rdCP
Fig.7 A 3rd-order CPPLL

Finally, the PLL becomes a 3rd-order system. Don’t worry about the phase margin too much, as long as the zero, the unity-gain frequency, and the 3rd pole are positioned well (Fig.8).

3pole_bodeplot
Fig.8 Gain plot of a 3rd-order CPPLL

The author refers to two books for writing this post: 1) Behzad Razavi, Design of analog CMOS Integrated Circuits; 2) Ali Hajimiri and Thomas H. Lee, The design of low noise oscillators.

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