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 Memos on FFT With Windowing
 Capacitor as a DiscreteTime Resistor
 A Brief Review On the Orders of PLL
 Stabilizing a 2Stage Amplifier
 Gm/ID versus IC
 Go Moderate
 The Calculation of Phase Margin
 Gm/IdDesign Methodology
 Brief Study of NoiseShaping SAR ADC – Part C
 Brief Study of NoiseShaping SAR ADC – Part B
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Author Archives: Dai
Memos on FFT With Windowing
Coherent sampling is quite difficult to meet under the lab conditions. One has to go for windowing to characterize the dynamic performance of ADC. Though seminal papers and reports [12] lie on my desk for quite long time, I still feel … Continue reading
Capacitor as a DiscreteTime Resistor
Prof. Ali has a column called “Circuit Intuitions” in the IEEE SolidState Circuits Magazine. This time he wrote about capacitor as a resistor, which is quite helpful for me to understand this property recognized by James Clerk Maxwell 140 years … Continue reading
A Brief Review On the Orders of PLL
The simplest PLL, as is shown in Fig.1, consists of a phase detector (PD) and a voltage controlled oscillator (VCO). Via a negative feedback loop, the PD compares the phases of OUT and IN, generating an error voltage that varies … Continue reading
Posted in Analog Design, Circuit Analysis
Tagged PLL, PLL phase error, PLL stability
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Stabilizing a 2Stage Amplifier
To stabilize an amplifier is not an easy task. At least for me, I used to be a spice slaver — mechanically change some components’ parameter and run a simulation to check the result, and again and again and again … until … Continue reading
Posted in Analog Design
Tagged 2stage folded cascode, Ahuja compensation, Miller compensation, Stability
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Gm/ID versus IC
According to the EKV model, the inversion coefficient, IC, is defined by the ratio of drain current to a specified drain current, IDSspec, where VGSVT = 2n*kT/q [1]. In order to know the IC, I have to set up a separate testbench to … Continue reading
Posted in Analog Design, MOS Models
Tagged EKV, gm/ID, Inversion Coefficient, moderate inversion
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Go Moderate
Either Prof. Sansen’s inversion coefficient (IC) approach or Prof. Murmann’s Gm/Id design methodology is telling the same story of poweraware analog design. With the help of Gm/Id design kit, I can easily visualize the transistor performance as a function of its gatesource voltage … Continue reading
The Calculation of Phase Margin
Negative feedback is ubiquitous, and the discussion on its stability can be found everywhere. For ease of reference, I will put a memo on the equations to calculate the phase margin. The amplifying system may includes multiple poles: . Neglecting higher … Continue reading