## Leading Simulators for Analog/RF Circuits

Recently I have the opportunity to touch some RF design. WoW, some simple metal lines need a fancy tool to get them modeled! WoW, both Windows and Unix tools are involved to simulate the EVM! It seems that Cadence Spectre … Continue reading

## Pulse Generator of Asynchronous SAR ADC

When it comes to designing SAR ADC, I am like a tortoise and can never imagine the world of rabbits. Recently I got some time to ponder how the rabbits can run so fast. One of the critical factors is … Continue reading

Posted in Data Converter | 1 Comment

## Ringing in Step Response

Is it possible to tell the stability of a negative-feedback circuit by just looking at its step response? The answer is yes. In this post, I will try to find the relationship between phase margin and ringing in step response. I … Continue reading

## Memos on FFT With Windowing

Coherent sampling is quite difficult to meet under the lab conditions. One has to go for windowing to characterize the dynamic performance of ADC. Though seminal papers and reports [1-2] lie on my desk for quite long time, I still feel … Continue reading

## Capacitor as a Discrete-Time Resistor

Prof. Ali has a column called “Circuit Intuitions” in the IEEE Solid-State Circuits Magazine. This time he wrote about capacitor as a resistor, which is quite helpful for me to understand this property recognized by James Clerk Maxwell 140 years … Continue reading

## A Brief Review On the Orders of PLL

The simplest PLL, as is shown in Fig.1, consists of a phase detector (PD) and a voltage controlled oscillator (VCO). Via a negative feedback loop, the PD compares the phases of OUT and IN, generating an error voltage that varies … Continue reading

## Stabilizing a 2-Stage Amplifier

To stabilize an amplifier is not an easy task. At least for me, I used to be a spice slaver — mechanically change some components’ parameter and run a simulation to check the result, and again and again and again … until … Continue reading

Posted in Analog Design | | 4 Comments

## Gm/ID versus IC

According to the EKV model, the inversion coefficient, IC, is defined by the ratio of drain current to a specified drain current, IDSspec, where VGS-VT = 2n*kT/q [1]. In order to know the IC, I have to set up a separate testbench to … Continue reading

Posted in Analog Design, MOS Models | | 1 Comment

## Go Moderate

Either Prof. Sansen’s inversion coefficient (IC) approach or Prof. Murmann’s Gm/Id design methodology is telling the same story of power-aware analog design. With the help of Gm/Id design kit, I can easily visualize the transistor performance as a function of its gate-source voltage … Continue reading

## The Calculation of Phase Margin

Negative feedback is ubiquitous, and the discussion on its stability can be found everywhere. For ease of reference, I will put a memo on the equations to calculate the phase margin. The amplifying system may includes multiple poles: . Neglecting higher … Continue reading

Posted in Analog Design | | 3 Comments