# Category Archives: Analog Design

## CMOS Single Stage

Found an old drawing on CMOS single stage from many years ago.  Stay healthy!

## Basics On Active-RC Low-Pass Filters

Just some basic understandings on analog filters which is inspired by ‘The Guru’ in our company. To clarify my thoughts, I will write in the format of Q&A. There are four questions to answer: What do we dream for a … Continue reading

## Leading Simulators for Analog/RF Circuits

Recently I have the opportunity to touch some RF design. WoW, some simple metal lines need a fancy tool to get them modeled! WoW, both Windows and Unix tools are involved to simulate the EVM! It seems that Cadence Spectre … Continue reading

## Ringing in Step Response

Is it possible to tell the stability of a negative-feedback circuit by just looking at its step response? The answer is yes. In this post, I will try to find the relationship between phase margin and ringing in step response. I … Continue reading

## Capacitor as a Discrete-Time Resistor

Prof. Ali has a column called “Circuit Intuitions” in the IEEE Solid-State Circuits Magazine. This time he wrote about capacitor as a resistor, which is quite helpful for me to understand this property recognized by James Clerk Maxwell 140 years … Continue reading

## A Brief Review On the Orders of PLL

The simplest PLL, as is shown in Fig.1, consists of a phase detector (PD) and a voltage controlled oscillator (VCO). Via a negative feedback loop, the PD compares the phases of OUT and IN, generating an error voltage that varies … Continue reading

## Stabilizing a 2-Stage Amplifier

To stabilize an amplifier is not an easy task. At least for me, I used to be a spice slaver — mechanically change some components’ parameter and run a simulation to check the result, and again and again and again … until … Continue reading

Posted in Analog Design | | 4 Comments

## Gm/ID versus IC

According to the EKV model, the inversion coefficient, IC, is defined by the ratio of drain current to a specified drain current, IDSspec, where VGS-VT = 2n*kT/q [1]. In order to know the IC, I have to set up a separate testbench to … Continue reading

Posted in Analog Design, MOS Models | | 1 Comment

## Go Moderate

Either Prof. Sansen’s inversion coefficient (IC) approach or Prof. Murmann’s Gm/Id design methodology is telling the same story of power-aware analog design. With the help of Gm/Id design kit, I can easily visualize the transistor performance as a function of its gate-source voltage … Continue reading

## The Calculation of Phase Margin

Negative feedback is ubiquitous, and the discussion on its stability can be found everywhere. For ease of reference, I will put a memo on the equations to calculate the phase margin. The amplifying system may includes multiple poles: . Neglecting higher … Continue reading

Posted in Analog Design | | 3 Comments