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 A Brief Review On the Orders of PLL
 Stabilizing a 2Stage Amplifier
 Gm/ID versus IC
 Go Moderate
 The Calculation of Phase Margin
 Gm/IdDesign Methodology
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Category Archives: Analog Design
A Brief Review On the Orders of PLL
The simplest PLL, as is shown in Fig.1, consists of a phase detector (PD) and a voltage controlled oscillator (VCO). Via a negative feedback loop, the PD compares the phases of OUT and IN, generating an error voltage that varies … Continue reading
Posted in Analog Design, Circuit Analysis
Tagged PLL, PLL phase error, PLL stability
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Stabilizing a 2Stage Amplifier
To stabilize an amplifier is not an easy task. At least for me, I used to be a spice slaver — mechanically change some components’ parameter and run a simulation to check the result, and again and again and again … until … Continue reading
Posted in Analog Design
Tagged 2stage folded cascode, Ahuja compensation, Miller compensation, Stability
2 Comments
Gm/ID versus IC
According to the EKV model, the inversion coefficient, IC, is defined by the ratio of drain current to a specified drain current, IDSspec, where VGSVT = 2n*kT/q [1]. In order to know the IC, I have to set up a separate testbench to … Continue reading
Posted in Analog Design, MOS Models
Tagged EKV, gm/ID, Inversion Coefficient, moderate inversion
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Go Moderate
Either Prof. Sansen’s inversion coefficient (IC) approach or Prof. Murmann’s Gm/Id design methodology is telling the same story of poweraware analog design. With the help of Gm/Id design kit, I can easily visualize the transistor performance as a function of its gatesource voltage … Continue reading
The Calculation of Phase Margin
Negative feedback is ubiquitous, and the discussion on its stability can be found everywhere. For ease of reference, I will put a memo on the equations to calculate the phase margin. The amplifying system may includes multiple poles: . Neglecting higher … Continue reading
Gm/IdDesign Methodology
Three times of entering a wrong password to access this site… Earlier in 2012, I wrote an introductory post about EKV model and later extended the related topic a little bit in another post – Stay Simple – SquareLaw Equation … Continue reading
Noise Effect On The Probability of Comparator Decision
In the previous post, it is explained why normal distribution with a standard deviation of is used to characterize the circuit inputreferred noise. In this post, we will calculate the probability of comparator decision (High or Low) with the existence of noise. We … Continue reading
Posted in Analog Design
Tagged Normal Distribution, Probability of Comparator Decision, Thermal Noise
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