Category Archives: Analog Design

CMOS Single Stage

Posted on September 17, 2020 by Dai

Found an old drawing on CMOS single stage from many years ago.  Stay healthy!

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Basics On Active-RC Low-Pass Filters

Posted on February 19, 2020 by Dai

Just some basic understandings on analog filters which is inspired by ‘The Guru’ in our company. To clarify my thoughts, I will write in the format of Q&A. There are four questions to answer: What do we dream for a … Continue reading →

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Leading Simulators for Analog/RF Circuits

Posted on December 2, 2019 by Dai

Recently I have the opportunity to touch some RF design. WoW, some simple metal lines need a fancy tool to get them modeled! WoW, both Windows and Unix tools are involved to simulate the EVM! It seems that Cadence Spectre … Continue reading →

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Ringing in Step Response

Posted on March 13, 2018 by Dai

Is it possible to tell the stability of a negative-feedback circuit by just looking at its step response? The answer is yes. In this post, I will try to find the relationship between phase margin and ringing in step response. I … Continue reading →

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Capacitor as a Discrete-Time Resistor

Posted on October 29, 2017 by Dai

Prof. Ali has a column called “Circuit Intuitions” in the IEEE Solid-State Circuits Magazine. This time he wrote about capacitor as a resistor, which is quite helpful for me to understand this property recognized by James Clerk Maxwell 140 years … Continue reading →

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A Brief Review On the Orders of PLL

Posted on August 11, 2017 by Dai

The simplest PLL, as is shown in Fig.1, consists of a phase detector (PD) and a voltage controlled oscillator (VCO). Via a negative feedback loop, the PD compares the phases of OUT and IN, generating an error voltage that varies … Continue reading →

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Stabilizing a 2-Stage Amplifier

Posted on November 10, 2016 by Dai

To stabilize an amplifier is not an easy task. At least for me, I used to be a spice slaver — mechanically change some components’ parameter and run a simulation to check the result, and again and again and again … until … Continue reading →

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Gm/ID versus IC

Posted on August 26, 2016 by Dai

According to the EKV model, the inversion coefficient, IC, is defined by the ratio of drain current to a specified drain current, IDSspec, where VGS-VT = 2n*kT/q [1]. In order to know the IC, I have to set up a separate testbench to … Continue reading →

Posted in Analog Design, MOS Models | Tagged , , , | 1 Comment

Go Moderate

Posted on August 7, 2016 by Dai

Either Prof. Sansen’s inversion coefficient (IC) approach or Prof. Murmann’s Gm/Id design methodology is telling the same story of power-aware analog design. With the help of Gm/Id design kit, I can easily visualize the transistor performance as a function of its gate-source voltage … Continue reading →

Posted in Analog Design, MOS Models | Tagged , , | 2 Comments

The Calculation of Phase Margin

Posted on August 3, 2016 by Dai

Negative feedback is ubiquitous, and the discussion on its stability can be found everywhere. For ease of reference, I will put a memo on the equations to calculate the phase margin. The amplifying system may includes multiple poles: . Neglecting higher … Continue reading →

Posted in Analog Design | Tagged , , | 3 Comments