I can find lots of reference on Smith chart online, among which one of the most useful one is explained by Prof. F. Delssperger and he also develops a handy software to help us with matching and etc. After reading his slides, I kind of understand that Smith chart is trying to combine the impedance in Z plane with the reflection coefficient in Polar diagram. However, I am still confused about the exact size and position of the circles until I happen to find this derivation.

I extract the main flow of derivations here. For details, please click the above link.

First, the reflection coefficient is a complex number.

Second, this coefficient corresponds directly to a specific impedance as seen at the point it is measured. It can be calculated based on a load impedance Z_{L} (using a reference impedance Z_{0}). And the load impedance is further normalized to the reference impedance z_{L}=Z_{L}/Z_{0}.

Third, the normalized load impedance, which is also a complex number, can be expressed by the reflection coefficient.

Fourth, after rationalizing, the normalized load resistance z_{R} and load reactance z_{I} can be expressed by the following two circle equations.

Finally, thanks to the author’s derivation, the equations of the two circle can be rewritten in a familiar format.

**For normalized load resistance:**

**For normalized load reactance:**

Now we can draw some circles on Smith chart.

]]>**Operation of CML latch**

Figure 1 shows a simplified block diagram of divider-by-2 and a CML (current-mode logic) latch. M_{1}/M_{2} form a preamplifier and M_{3}/M_{4} a cross-coupled pair. Fig. 2 illustrates the low-frequency and high-frequency operation of CML latch. During the low-frequency operation, when CK is high, the input is amplified by M_{1}/M_{2}; when CK goes low, the cross-coupled pair performs regeneration and latches the state. For short cycle operation, the cross-coupled pair continues to provide gain in the store mode, regenerating to a final differential output of I_{ss}*R_{L}. This condition is met if g_{m3}R_{L}>1.

**Speed estimation of CML latch**

When CK is high, the circuit can be viewed as a single-pole amplifier. Assume that a step voltage is applied at the input, the differential output voltage can be expressed as

where V_{XY0} and V_{XY1} are the initial and final differential output during the sense phase, g_{m1} is the transconductance of the input transistor, the product of R_{L} and C_{L} is the time constant. R_{L} and C_{L} are the equivalent resistive and capacitive load seeing from node X/Y.

As is shown in Fig.2, in a divider-by-2, input of one latch is output of the other. Both the initial differential voltage at X/Y (V_{XY0}) and the input voltage step (V_{step}) have the same value of I_{ss}*R_{L}. Replacing V_{XY0} and V_{step} with I_{ss}*R_{L}, Eq(1) can be rewritten as

When clock goes low, the latch starts regeneration and the differential output continues to evolve, which can be expressed as

The regenerative time constant equals

where g_{m3} is the transconductance of the cross-coupled pair. The latch regenerates the differential output to a final value of -I_{ss}*R_{L}. Replacing V_{XY2} with -I_{ss}*R_{L}, Eq(3) can be rewritten as

Now we have derived the amplification time, Eq(2), and the regeneration time, Eq(5), respectively. It would be interesting to visualize them in the following plots (Fig.3 and Fig.4). It can be seen that the optimal speed happens when the differential output at the end of the sense phase (V_{XY1}) is between its final settled value and half of it.

The above plots are based on the following assumptions:

- Gm/Id: a value of 10 is a good start. This indicates that operating the transistor in moderate inversion is optimal when we value speed and power efficiency equally. The conversion between Gm/Id and inversion coefficient(IC) can be referred to this post.
- Gain (G): a value around 3 is a good start. For submicron CMOS node, the self-gain of a standard transistor with minimum length is normally no large than 10. In this case, we further assume M
_{1}/M_{2}and M_{3}/M_{4}have the same size. - Differential output voltage (I
_{ss}*R_{L}): in the range of 400 ~ 600 mV [2]. - Tail current (I
_{ss}): assume R_{L}is 500Ohm, I_{ss}around 800uA is a good start point. Then g_{m}= Gm/Id*(I_{ss}/2) = 10*400uA = 4 mA/S. (Note that g_{m}R_{L}> 1 holds) - Transistor width (W): according to gm/Id simulation of a minimum-length transistor in submicron process, for 1-um width a gm/Id of 10 needs ~150-uA bias current. If the width is 4x, the bias current will be 600uA.
- Capacitive load (C
_{L}): the capacitive load contributed by the transistors are equal to 2*Cgg+2*Cdd ~= 3Cgg. With width of 4um and length of 30nm, the Cgg can be approximated to about 2.4fF (4*0.03*20=2.4fF). Normally, the load from a succeeding buffer will dominate.

The Matlab script used to plot the data can be found here.

References:

[1] Online lecture notes (Access Jan.05, 2021), https://people.engr.tamu.edu/spalermo/ecen620/lecture12_ee620_dividers.pdf

[2] B. Razavi, “The Cross-Coupled Pair – Part II [A Circuit for All Seasons],” IEEE Solid-State Circuits Magazine, Issue 4, pp. 9-12, Fall 2014.

]]>```
%%%%%%%%%%%%%%% Estimate the speed of CML Latch %%%%%%%%%%%%%%%%%%%%%
clear all; clc;
% Initial settings
G = 3; % Amplification gain
gm_id = 10; % Inversion coefficient
id_unit = 150e-6; % Id for gm_id=10 at W = 1um, L=30nm
cg_unit = 0.4e-15; % Cgg at W = 1um
ll = 0.03; % Transistor length in um
ww = 4; % Transistor width
id = id_unit*ww; % Bias current
gm = gm_id*id; % Transistor transconductance
cg = ww*cg_unit; % Gate capacitance in F
cpar = 10e-15; % parasitic capacitance
cl = 3*cg + cpar; % Total load capacitor
rl = G/gm; % Resistor load
iss = id*2; % Tail current
deltaV = rl*iss; % Differential output voltage
tau = rl*cl; % Time constant
k = 1:0.2:8; % Ratio of Iss*RD/Vxy1
t1 = -tau.*log(1-(1+1./k)./G).*1e12; % Amplification time in ps
t2 = tau./(G-1).*log(k).*1e12; % Regeneration time in ps
plot(k, t1, '-rd', k, t2, '-bo', k, t1+t2, '-k+')
xlabel('-I_{ss}R_D/V_{XY1}'); ylabel('Time [ps]');
xlim([1 max(k)]);
title(sprintf('Gm/Id = %.0f; G = %d; W = %d [um]; C_L = %.0f [fF] \n R_L = %.0f [Omh]; I_{SS} = %.0f [uA]; V_{diffo} = %.1f [mV]', gm_id, G, ww, cl*1e15, rl, iss*1e6, deltaV*1e3));
legend('Amplification time', 'Regeneration time', 'Total sum', 'Location', 'Best');
grid on;
```

```
```

Boron is a “Group 3” element. It has 3 valence electrons in its outmost shell. Once it is introduced into the silicon lattice it will bond to the nearby silicon atoms with the traditional double bonds, and produce a hole which will accept electrons and migrate around. The hole concentration (p) is approximate to the density of Boron atoms.

Phosphorus is a “Group 5” element. It has 5 valence electrons in its outmost shell. Once it is bonded to the nearby silicon it will produce a free electron and the electron acts as a donor. The electron concentration (n) is approximate to the density of Phosphorus atoms.

Note that the product of n and p is constant, which is equal to n_{i}^{2}.

Finally, an interesting question quoted from Prof. Razavi’s Youtube video on Electronics:

Q: What happens to n and p in n-type silicon as T increases?

A: n keeps constant and p increases as T increases.

The diagram below shows positive charge travels from the left to the right of silicon. At t1, one electron is released which produces a positive charge (indicated as a hole); at t2, the second electron is released and trapped in the hole shown in t1; at t3, the third electron is released and again trapped in the hole shown in t2.

This explains why movement of holes is shower than that of electrons.

For pure silicon, the density of holes is equal to the density of electrons (n_{i}).

Covalent bonding in silicon:

Its resistivity drops as temperature rises.

Density of free electrons in silicon can be calculated as:

At T=300K,

In the same cubic, there are 5×10^{22} silicon atoms. The ratio of electrons to silicon atoms is tiny tiny…Hence we need to do something to make it conducting.

Most of the information is gathered after watching the youtube video from Prof. Behzad Razavi’s Electronics 1. He is really talented at explaining things. If you have time, just skip mine and watch his video.

]]>Somewhat make sense!

This triggers me to think about the keywords in my field – IC design. Astonishingly, some words are so common to me but I can’t tell the real details. Am I already a professional?! Maybe I can start a similar project in the dark cold Covid nordic winter to cheer up a little bit

100 is not an absolute number to target, but in the beginning, let’s say 100. In addition, two or three days is also mission impossible for me, maybe two or three years…

Anyway, keep thinking and keep writing!

]]>

Stay healthy!

]]>Just some basic understandings on analog filters which is inspired by ‘The Guru’ in our company. To clarify my thoughts, I will write in the format of Q&A. There are four questions to answer:

- What do we dream for a low-pass (LP) filter?
- Why complex poles are required?
- How to generate complex poles without inductor?
- Any real-life example?

**Q1) What do we dream for a low-pass (LP) filter?**

An ideal one, which has a brick-wall response. We only receive what we intend to receive, pure and loss-free. But, in reality…

**Q2) Why complex poles are required?**

Complex poles help to lift up the magnitude around the cut-off frequency by contributing larger pole quality factor (Q).

If we only have real poles, though higher-order gives better roll-off, the loss of magnitude around cut-off frequency becomes bigger.

Now we move to a system which has complex poles. Taking the 5th-order Butterworth filter as an example, which has a real pole and two pairs of complex poles, the complex poles with a Q of 1.618 help to compensate the loss of magnitude around cut-off frequency. It tries to approximate the brick-wall response.

**Q3) How to generate complex poles without inductor?**

The answer is Feedback! R and C only generate real poles. When feedback is applied around a system containing real roots, the closed-loop transfer function may contain complex roots.

Let’s think of this example: an amplifier with two poles. Its transfer function can be written as:

.

The poles are generated by Rs and Cs in the amplifier and they are real. Now assume a negative feedback of beta is placed around the amplifier. The closed-loop transfer function becomes:

.

We can then calculate the two poles of the closed-loop transfer function:

.

By increasing , complex poles can be achieved!

**Q4) Any real-life example?**

Of course. Fig.4 shows the Two-Thomas biquad. Without the feedback resistor R2, the open-loop transfer function has two real poles: one pole generated by R3 and C1 and the other pole at origin. With a feedback resistor applied, the two poles will move towards each other, arrive at the same position, and then leave the real axis, becoming complex poles.

]]>It seems that Cadence Spectre just can’t do it on its own any more. Really? I start to ask myself which simulator or which way of simulation is more efficient for my design. Then I found this paper published in 2014, titled “Overview of Commercially-Available Analog/RF Simulation Engines and Design Environment”. Yep, it’s helpful (at least to a RF newbie). It reviews four main analog/RF simulators on the market:

- Cadence Spectre
- Agilent ADS (now Keysight, which was spun off from Agilent in 2014)
- Agilent GoldenGate (again now Keysight)
- Mentor Graphics AFS

Cadence Spectre, an evolved engine from SPICE, is good at transient analysis. However, the transient analysis may become expensive when it deals with RF signals, the signals normally containing a periodic high-frequency carrier and a low-frequency modulation signal. The carrier forces a small time step while the signal forces a long simulation interval. To speed up the RF simulation, harmonic balance (HB) comes in, which works on frequency domain. Though ADS provides a best-in-class HB simulator for RF design, its layout suite is inferior to Cadence Virtuoso environment. Hence the Spectre simulator is still widely used as the standard sign-off simulator. Recently, to leverage ADS for RF simulation and Cadence for schematic capture and layout, GoldenGate is highly integrated into the Cadence design flow as an efficient hybrid method.

It is obvious that which simulator to choose depends pretty much on the signal nature. In general, for circuits with a few frequency components, like LNA and mixer, the frequency-domain technique is more efficient, while time-domain technique is more efficient for circuits with abrupt edges, like ADC/DAC or control logics. Many interesting details are described in the paper. Fig.1 provides a short summary.

Fig.1 A short performance summary [1]

Note that MTS is the acronym of multi-technology simulations. We typically design circuits within a single design kit. However, for some RF products, they may be composed of different modules from different processes. According to the paper, Cadence’s ADE GXL can do MTS simulations.

Reference:

[1] B. Wan and X. Wang, “Overview of commercially-available analog/RF simulation engines and design environment,” *12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)*, 2014.