Go Moderate

Either Prof. Sansen’s inversion coefficient (IC) approach or Prof. Murmann’s Gm/Id design methodology is telling the same story of power-aware analog design.

With the help of Gm/Id design kit, I can easily visualize the transistor performance as a function of its gate-source voltage (see Fig.1). As VGS increases, the transistor undergoes the weak, the moderate, and the strong inversion. For high gain, we go left; for high speed, we go right. Being far-left, the gain is not increasing but the speed drops extremely low; being far-right, the speed is not increasing but the drain current is still climbing! For a decent figure-0f-merit (speed*gain), go to the middle, go moderate!

Fig.1 ID, gm, gm/ID, fT, fT*gm/ID as a function of VGS at fixed VDS, VBS, and W/L

As CMOSers, we love the square-law equation, we sometimes hate and sometimes embrace the exponential subthreshold current equation. But with regard to the current flowing between the strong and the weak, do we have one equation for it? No, but yes…by doing some math, the EKV model combines all the three. Referring to [1], the IC-V related equations are copied as follows:

$e^{\sqrt{IC}} = e^v+1$,

$IC = \frac{I_{DS}}{I_{DSspec}}$,         $v = \frac{V_{GS}-V_T}{2nU_T}$,

$I_{DSspec} = (\frac{\mu C_{OX}}{2n})(\frac{W}{L})(2nU_T)^2$,

where n is subthreshold slope factor and UT is thermal voltage. At room temperature, 2nUT is about 70mV [1]. As Fig.2 shows, the IC-V curve matches well with the weak for IC < 0.1 or the strong for IC > 10; the moderate locates where IC is between 0.1 and 10.

Fig.2 Normalized overdrive voltage as a function of inversion coefficient

Reference

[1] W. Sansen, “Minimum power in analog amplifying blocks – presenting a design procedure ”, IEEE Solid-State Circuits Magazine, fall 2015.

The Calculation of Phase Margin

Negative feedback is ubiquitous, and the discussion on its stability can be found everywhere. For ease of reference, I will put a memo on the equations to calculate the phase margin.

Fig.1 The symbolized feedback configuration

The amplifying system may includes multiple poles:

$A(s)=\frac{A_0}{(1+\frac{s}{\omega_{p1}})(1+\frac{s}{\omega_{p2}})(1+\frac{s}{\omega_{p3}})(...)}$.

Neglecting higher order terms, it could be simplified to a two-pole equation: one dominant pole and one equivalent non-dominant pole which is approximate to:

$\frac{1}{\omega_{eq}}=\frac{1}{\omega_{p2}}+\frac{1}{\omega_{p3}}+...$.

The frequency of interest is where the loop gain magnitude is close to unity, denoted as ωt. Normally ωt is much larger than the dominant pole. Hence, βA(s) around ωt can be further simplified to:

$\beta A(s)=\frac{\beta A_0 \omega_{p1}}{s(1+\frac{s}{\omega_{eq}})}$.

Considering the first pole introduces -90° phase shift, the phase of the loop gain at ωt is:

$Phase_{Loop Gain} = -90^o-tan^{-1}(\frac{\omega_t}{\omega_{eq}})$.

Consequently, the phase margin (PM) is calculated by adding 180° to the phase of the loop gain and it is written as:

$PM \approx 90^o-tan^{-1}(\frac{\omega_t}{\omega_{eq}}) = tan^{-1}(\frac{\omega_{eq}}{\omega_t})$.

It can be seen that the phase margin is determined by the relative position between the equivalent non-dominant pole and the unity loop gain bandwidth.

ωeq/ωt        0.5               1               2               3               4

PM            26.6°          45°          63.4°         71.6°         76°

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Gm/Id-Design Methodology

Three times of entering a wrong password to access this site…

Earlier in 2012, I wrote an introductory post about EKV model and later extended the related topic a little bit in another post – Stay Simple – Square-Law Equation Related. Since then I keep following the information about the EKV model and the inversion-coefficient-based analog design methodology.

One of the major contributors on this design methodology is Prof. Willy Sansen. He has given a short tutorial named Impact of Scaling on Analog Design. The tutorial was organized by ISSCC through edX (free access after registration). Most recently he also published an article [1] to summarize his idea in the IEEE Solid-State Circuits Magazine.

The journey starts with a beautiful equation which nicely links the weak and the strong inversion (see the curve in Fig.1).

Fig.1 The relationship between V and IC

Fascinated by Prof.Sansen’s design procedure, I tried to apply it to my daily design work. Theoretically, it does give me a broader view and some insight on the low-power design. However, practically I find it difficult to make full use of it. Especially nowadays most of the design enters into the deep submicron region, and the model parameters are so complicated to interpret.

Then there comes another big guy – Prof. Boris Murmann. Yes, the professor provides the famous ADC performance survey! Now the professor also launches his gm/Id starter kit. The kit provides scripts that can co-simulate between SPICE simulator and Matlab and store transistor DC parameters into Matlab files. The data stored can then be used for systematic circuit design in Matlab. It looks brute-force but yet smart and efficient!

It’s free. Enjoy!

Reference

[1] W. Sansen, “Minimum power in analog amplifying blocks – presenting a design procedure ”, IEEE Solid-State Circuits Magazine, fall 2015.

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Brief Study of Noise-Shaping SAR ADC – Part C

The topic of noise-shaping SAR ADC will come to an end in this post. In Part A, I briefly talked about the concept of noise shaping applied to sigma-delta modulators. In Part B, I introduced one special property of SAR ADCs which can be utilized to perform noise-shaping – the SAR architecture can generate the conversion residue without a feedback DAC. Then some form of noise shaping was achieved, but the result was not so satisfactory. In this post, I will continue the journey.

A small summarize of performing noise shaping on the SAR architecture from Part B:

1. let the DAC array complete all the switching based on the decisions from MSB to LSB (the conversion residue is generated)
2. sample the conversion residue ($V_{RES}$) on an extra capacitor
3. apply the residue with opposite sign ($-V_{RES}$) to the opposite terminal of the comparator

If the extra capacitor is much smaller than the array capacitor, the current residue is sampled and there is almost no memory effect. The linear model of the SAR ADC looks like:

Fig. 1 Linear model when residue sampling capacitor is much smaller than the array capacitor

If an integrator is added to Fig. 1, the noise transfer function NTF becomes identical to the 1st-order noise shaping:

Fig.2 Linear model after an integrator is added to the system

The corresponding hardware implementation could look like this:

Fig.3 Hardware implementation

1st-order noise shaping is finally achieved! BUT, circuit design is all about compromise. There are some concerns. Just list some of them as follows:

1. kT/C_R is not noise-shaped anymore
2. of course, you can never get an amplifier with infinite gain
3. residue attenuation due to charge sharing between sampling capacitor and parasitic capacitor at the amplifier input
4. switch-induced error

I would like to stop here (because weekend is coming ;-).

If you want to know more about practical solutions. I recommend the interesting and well-written paper [1]. I would like to thank the authors. I enjoyed a lot reading their paper.

References:

[1] J. A. Fredenburg and M. P. Flynn, “A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-shaping SAR ADC”, JSSC, vol.47, 2012.

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Brief Study of Noise-Shaping SAR ADC – Part B

In the previous post, I’ve shared some basics of sigma-delta ADC. In this post, before we look at the noise-shaping SAR ADC, let’s again do a warm-up.

The z-domain linear model for a 1st-order sigma-delta modulator:

Fig.1 Linear model of a 1st-order sigma-delta modulator

The linear model has the same transfer functions as the one in Fig.6 of the previous post, where a delaying integrator is used as the loop filter.

Before the quantizer, the modulator is doing two tasks:

1. Δ: generate the conversion residue R (=U-V)

2. : add all the previous residues

Keep this in mind. Now let’s try to make the SAR do the noise shaping.

A conventional charge-redistribution SAR ADC:

Fig. 2 Charge-redistribution SAR ADC

When the conversion is complete for an N-bit SAR, the magnitude of the voltage generated at the top plate of the DAC represents the difference between the sampled input and a representation constructed from decisions of the high-weighted N-1 bits:

$V_{DAC} = \frac{V_{REF}}{2}D_{N-1}+\frac{V_{REF}}{2^2}D_{N-2}+\cdots+\frac{V_{REF}}{2^{N-1}}D_1-V_{IN}$

If we do one extra switching of the DAC array based on the final decision of LSB, we recalculate the voltage generated at the DAC top plate:

$V_{DAC}^{+1} = \frac{V_{REF}}{2}D_{N-1}+\cdots+\frac{V_{REF}}{2^{N-1}}D_1+\frac{V_{REF}}{2^N}D_0-V_{IN}$

Yes! We catch the conversion residue! It is further simplified as follows:

$V_{RES} = D_{OUT}-V_{IN}$

According to Fig.1, the simplified equation can be rewritten as $-V_{RES} = V_{IN}-D_{OUT}$.

Then we need to sample this residue and store it somewhere else. How about this method?

Step 1: sample the residue on the extra capacitor

Fig.3 Sample the residue on the extra capacitor (discrete-time domain is used to indicate the current sample and the previous one)

Step2: apply the sampled residue to the opposite input of the comparator during the next conversion

Fig.4 Apply the residue to the opposite input of the comparator when the next sample is converted

Now it comes to the discussion about choosing the value of C_R.

Assume $C_R = k C_{DAC}$

Then $V_R(n) = k_1 V_{RES}(n) + k_2 V_R(n-1)$,

$k_1=\frac{1}{1+k}$ and $k_2=\frac{k}{1+k}$

What will the linear model look like?

Fig. 5 Linear model and transfer functions

If  $C_R << C_{DAC}$ ($k \approx 0$ ),  $k_1 \approx 1$ and $k_2 \approx 0$. The memory of the previous residues is ignored and only the current residue is recorded. The linear model can be simplified to:

Fig. 6 Linear model and transfer functions when k1=1 and k2=0

Take a look at the magnitude responses of the NTFs under different k:

Fig. 5 Magnitude response of NTFs under different k and compared to 1st-order noise shaping

Noise does be shaped! In addition, it seems using a small residue sampling capacitor is fairly good compared to larger ones (Note that the kT/C noise during residue sampling presents itself to the comparator input and can also be shaped together with the quantization noise and the input-referred comparator noise [1]).

However, compared to the 1st-order modulator, this way of noise shaping is much less efficient. We could do better! How? The next post ;-).

References:

[1] J. A. Fredenburg and M. P. Flynn, “A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-shaping SAR ADC”, JSSC, vol.47, 2012.

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Brief Study of Noise-Shaping SAR ADC – Part A

Sometimes it is much easier to become a fan of something when you only know something about it. Just like Sigma-Delta ADC, it is so complicated that even though I have learned it for several times I still can’t fully understand it!

Nevertheless, I am still a fan of it ;-).

Sigma-Delta ADCs dominate in the high-resolution domain (though they are not extremely fast, actually kind of slow…).

Fig. 1 Signal-to-noise-and-distortion ratio (SNDR) versus sampling frequency of Sigma-Delta ADCs and other Nyquist ADCs (SAR, Pipeline, and Flash). The data were reported in ISSCC, and collected by Murmann’s ADC survey [1].

I am currently doing successive-approximation-register (SAR) ADC.

SAR ADCs are quite energy-efficient, but less accurate than Sigma-Delta ADCs.

Fig. 2 Energy (P/fs) versus SNDR of SAR ADCs, Sigma-Delta ADCs, and other Nyquist ADCs (Pipeline and Flash). The data were again extracted from Murmann’s ADC survey [1].

In order to achieve high resolution, can SARs shape the noise just as Sigma-Delta ADCs do?

People have tried to imploy noise-shaping technique into the SAR architecture [2, 3], but so far the reported performance (with chip measurement) is not very compelling (SNDR = 62dB , Power = 806uW, Bandwidth = 11MHz, FoM = 35.8fJ/conv) [3].

Nevertheless, the idea of noise-shaping SAR is so intriguing.

Before entering into this topic, I would like to do some warm-ups – some basics of Sigma-Delta ADCs (yes, that’s all I know about it).

Some basics of Sigma-Delta ADCs:

1. Oversampling

Fig.3 Brief illustration of oversampling (OSR is the abbreviation of oversampling ratio)

Doubling the sampling frequency gives 3 dB increase of SNR. However, oversampling is seldom used alone, and it is commonly used together with the noise-shaping technique.

2. Noise-shaping

Fig.4 Brief illustration of noise-shaping and the sigma-delta modulator

Filtering is introduced into the ADC to further suppress the in-band quantization noise power. At the same time, the filtering does not affect the input signal. By applying a loop filter before the quantizer and introducing the feedback, a sigma delta modulator is built.

3. Linear model of a sigma-delta modulator

Fig.5 Linear model of a sigma-delta modulator, STF and NTF are abbreviations of signal transfer function and noise transfer funcion, respectively. (More information can be referred to Schreier’s book[4])

According to STF and NTF, if the transfer function of the loop filter H(z) is designed to have a large gain inside the band of interest and small gain outside the band of interest, the signal can pass the modulator and the noise can be greatly reduced.

4. If an integrator is chosen to be the loop filter

Fig. 6 Modulator with an integrator as the loop filter and its STF and NTF

We do a plot of H(f), STF(f), and NTF(f) (Matlab ‘fvtool’ is used):

Fig. 7 Magnitude response of H(f), STF(f), NTF(f)

Bingo! The signal is passed to the output with a delay of a clock cycle, while the quantization noise is passed through a high-pass filter.

Doubling the sampling frequency gives 9 dB increase of SNR for 1st order noise shaping.

5. Get more aggressive on the order

Fig. 8 Magnitude response of NTF from 0th – 3rd order

This post tells the basic story of noise-shaping. In the next post, I will try to learn how noise-shaping can be used in SAR ADCs.

References:

[1] B. Murmann, “ADC Performance Survey 1997-2014,” [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html.

[2] K. S. Kim, J. Kim, and S. H. Cho, “nth-order multi-bit \Sigma-\Delta ADC using SAR quantiser”, Electronics Letters, vol. 46, 2010.

[3] J. A. Fredenburg and M. P. Flynn, “A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-shaping SAR ADC”, JSSC, vol.47, 2012.

[4] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, 2005.

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Noise Effect On The Distribution of ADC Output Codes

In the previous post, the probability of comparator decision with the existence of noise was calculated. In this post, the topic about noise and probability will continue. The whole topic is actually inspired by a 1986-paper [1], which discusses noise effect on the distribution of SAR ADC output codes. Following the author’s method, though I end up with slightly different results, still I found some interesting things which I would like post here.

Assume an input voltage of $V_i$ is applied to an ADC, and the ADC has input-referred noise with a standard deviation of $\sigma$. Then, the input voltage compares with certain reference voltage $V_r$ to determine the corresponding bit. Referring to the equations calculated in the previous post, the probability of the bit being high is written as

$P(D_j = 1)=\frac{1}{2} erfc(\frac{V_r-V_i}{\sqrt{2}~ \sigma})$.

Similarly the probability of the bit being low is given by

$P(D_j = 0)=\frac{1}{2} erfc(\frac{V_i-V_r}{\sqrt{2}~ \sigma})$.

Considering the time sequence of Nyquist ADCs when they generate the digital outputs, I roughly group them into two categories: outputs are converted simultaneously and outputs are converted successively. The former needs $2^N-1$ times comparison for N-bit, and the latter only needs $N$ times but with the penalty of speed. I’m more interested in the second case, lazy and slow but still doing the job ;-).

Problem formulation: Due to the existence of noise, the input voltage can be converted to erroneous output codes or a correct one (respectively indicated with yellow and blue backgrounds in Fig.1). Probabilities of each converted output code corresponding to one particular input are of interest.

Fig.1 An example of 3-bit ADC. Due to noise, the input can be mapped to erroneous output codes (with yellow background) or a correct one (with blue background). The probability for each mapping is of interest.

How to calculate the probability of one particular output code?

Fig. 2 gives an example of probability calculation for code “100” converted by a 3-bit SAR ADC. The input voltage $V_i$ corresponds to code “101”. The calculation starts from MSB till LSB. The probability of less-significant bits will depend on the results of more-significant bits. Finally, the probability of a given code is the product of the probability of its individual bits.

Fig. 2 Probability calculation of code “100” generated by a 3-bit SAR ADC.

Knowing the way of calculating the probability of a given code, I tried to look at the noise specifications from statistics point of view. There are two noise specifications commonly used (in academia): noise power is equal to the quantization noise or noise standard deviation is equal to 1 LSB. The former introduces 3 dB loss of SNR, and the latter 11 dB. Then, how does the code distribution look like under these two specifications?

Noise power is equal to the quantization noise:

Fig. 3 Probability of output codes for a 10-bit SAR ADC with an analog input corresponding to code 510 + 1/4 LSB offset and input-referred noise power equal to its quantization noise.

Noise standard deviation is equal to 1 LSB:

Fig. 4 Probability of output codes for a 10-bit SAR ADC with an analog input corresponding to code 510 + 1/4 LSB offset and input-referred noise standard deviation equal to 1 LSB.

Sorry for the math. Like nonsense in the middle of a summar day. Sleepy?

Reference

[1] Philip W. Lee, “Noise considerations in high-accuracy A/D converters”, JSSC, 1986.