Tag Archives: gm/ID design methodology

Current-Mode-Logic (CML) Latch

It’s a rather old topic and one can find many good references. In this post, I will write down some of my basic understandings on this circuit. Operation of CML latch Figure 1 shows a simplified block diagram of divider-by-2 … Continue reading

Posted in Circuit Analysis | Tagged , | 2 Comments

Go Moderate

Either Prof. Sansen’s inversion coefficient (IC) approach or Prof. Murmann’s Gm/Id design methodology is telling the same story of power-aware analog design. With the help of Gm/Id design kit, I can easily visualize the transistor performance as a function of its gate-source voltage … Continue reading

Posted in Analog Design, MOS Models | Tagged , , | 2 Comments