To stabilize an amplifier is not an easy task. At least for me, I used to be a spice slaver — mechanically change some components’ parameter and run a simulation to check the result, and again and again and again … until the moment some basic analyses saved me! Same as the post on calculation of phase margin, I write a memo here for ease of reference.

1. **Usually the most difficult condition is unity-gain feedback.** As Fig.1 shows, the close-loop bandwidth is normally smaller than or equal to the unity-gain bandwidth. This means it reaches the maximum phase drop at the unity-gain point, making unity-gain feedback the most difficult for stability.

2. **Adding a miller capacitor between the two cascaded stages is a common technique. **As Fig.2 shows, K is the ratio between the second pole and the GBW, which determines the phase margin (referring to this post). In addition, to push the right-half-plane (RHP) zero far more than the second pole, it’s better to keep Cm much smaller than C2. This further puts a demand on the ratio between gm1 and gm2. Finally, the trade-off between noise/speed (small gm1) and current consumption (large gm2) lands on the desk (as expected).

3. **Introducing a nulling resistor is the most popular approach to mitigate the positive zero.** Compared to Fig.2, both the poles (neglecting the third non-dominant pole) and the GBW won’t change, except for the positive zero. How to calculate the new zero? Fig.3 demonstrates a simple way which was introduced by Prof. Razavi in his analog design book. One can either use the zero to (try to) cancel the second pole or simply push the zero to infinity.

4. **Ahuja compensation [1] is another way to abolish the positive zero.** The cause of the positive zero is the feedforward current through Cm. To abolish this zero, we have to cut the feedforward path and create a unidirectional feedback through Cm. Adding a resistor such as in Fig.3 is one way to mitigate the effect of the feedforward current. Another approach uses a current buffer cascode to pass the small-signal feedback current but cut the feedforward current, as is depicted in Fig.4. People name this approach after the author Ahuja.

5. **A good example of using Ahuja compensation is to compensate a 2-stage folded-cascode amplifier.** As is shown in Fig.5, by utilizing the “already existed” cascode stage, the Ahuja compensation can be implemented without any additional biasing current. There are two ways to put the miller capacitor, which normally will provide the same poles but different zeros. In REF[2], the poles and zeros of the two approaches are calculated based on reasonable assumption. Out of curiosity, I also drew the small-signal model and derived the transfer function. With some patience I finally reached the same result as given in REF[2].

6. **The bloody equations of poles and zeros of two Ahuja approaches are shared in Fig.6.** Though these equations looks very dry at the moment, one will appreciate them during the actual design. They do help me to stabilize an amplifier with varying capacitive load. One thing worth to look at is the ratio between the natural frequency of the two complex non-dominant poles and the GBW. Considering Cm and C2 are normally in the same order and C1 is much smaller, the ratio will end up with a relatively large value and the phase margin can be guaranteed.

Oh…finally, it took me quite some time to reach here. The END.

Reference:

[1] B.K.Ahuja, “An improved frequency compensation technique for CMOS operational amplifiers”, JSSC, 1983.

[2] U. Dasgupta, “Issues in “Ahuja” frequency compensation technique”, IEEE International Symposium on Radio-Frequency Integration Technology, 2009.

Great post, thanks.

Just a side question: did you draw the diagrams on paper and scanned them, or did you do it using a tablet of some sorts?

Thanks. I use the app from Apple store named Paper 53.